EVALUATING THE AD9467-FMC-250EBZ ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki] (2024)

This version (25 Apr 2023 13:29) was approved by Iulia Moldovan.The Previously approved version (05 Oct 2021 23:05) is available.

Table of Contents

• Full feature evaluation board for the AD9467

• SPI interface for setup and control

• Uses 12V. 3.3V from the FMC connection

• Internal and external reference options

• VisualAnalog® and SPI controller software interfaces

• AD9467 Data Sheet

• EVAL-SDP-CH1Z data capture kit SDP-H1

• AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual

• AN-878 Application Note, High Speed ADC SPI Control Software

• ADI SPI Application Note ADI Serial Control Interface Standard

• AN-835 Application Note, Understanding ADC Testing and Evaluation

• VisualAnalog

• SPIController

• FPGA bin file (Unzip before use)

• Schematics, Bill Of Materials, and Gerber Layout/Fabrication Files

• Analog signal source and antialiasing filter

• Sample clock source

• 12V, 2.5A switching power supply connected to the data capture board (SDP-H1)

• PC running Windows®

• USB 2.0 port

• AD9467-FMC-250EBZ board

• SDP-H1 FPGA-based data capture kit

Before using the software for testing, configure the evaluation board as follows:

1. Connect the AD9467-FMC-250EBZ evaluation board to the SDP-H1 data capture board, as shown in Figure 2.

2. Connect one 12V, 2.5A switching power supply (such as the one supplied) to the SDP-H1 board. Connect the Mini-B USB port of the SDP-H1 board to the PC with the supplied USB cable.

   See Also

   FMC에서 SLR(Specific License Reservation) 구성

3. The SDP-H1 will appear in the Device Manager as shown in Figure 3.

   Figure 3. Device Manager Showing SDP-H1

4. If the Device Manager does not show the SDP-H1 listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.

5. On the ADC evaluation board, provide a clean, low jitter 250MHz clock source to connector J201 and set the amplitude to 16dBm. This is the ADC Sample Clock.

6. On the ADC evaluation board, provide a clean, low jitter clock source to connector J100. Use a shielded, RG-58, 50Ohm, coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, pass filter with 50Ohm terminations and appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters)*.

*When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644B signal generators or equivalent*

1. Click Start All Programs Analog Devices VisualAnalog VisualAnalog.

2. On the VisualAnalog “New Canvas” window, click ADC Single AD9467 FFT.

   Figure 4. Selecting the AD9467 canvas

3. If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see Figure 5).

   Figure 5. Expanding the Display

4. Click the Settings button in the ADC Data Capture block as shown in Figure 6

   Figure 6. Changing the ADC Capture Settings

5. On the General tab make sure the clock frequency is set to 250MHz (or other clock frequency).

   Figure 7. Setting the clock frequency and capture length

6. Click on the Capture Board tab and browse to the ad9467_sdp_h1.bin file. Click the Program button. The FPGA_DONE LED should illuminate on the EVAL-SDP-CH1Z board indicating that the FPGA has been correctly programmed. The bin file is available at the ftp site ftp://ftp.analog.com/pub/HSC_ADC_Apps/SDP-H1/ad9467_sdp_h1.bin

7. Click OK

1. Click Start All Programs Analog Devices SPIController SPIController

   Figure 8. Control Window for AD9647

2. Select the AD9467_16Bit_250MSspiR03.cfg if prompted.

3. If necessary, click File Cfg Open AD9467_16Bit_250MSsspiR03.cfg

4. To enable SPI communications, click File Config Controller Dialog and un-check the SDO Active button

   Figure 9. Un-Selecting SDO Active in SPIController

1. Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 9

   Figure 10. AD9467-FMC-250 FFT at 5MHz Analog Input

2. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window). Usually about 16dBm of signal power from the signal generator will result in a -1dBFS Fundamental signal.

3. To save the FFT plot do the following

   1. Click on the Float Form button in the FFT window

      Figure 11. Floating the FFT window

   2. Click on File Save Form As button and save it to a location of choice

FFT plot appears abnormal

• If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.

• In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (Offset Binary by default).

The FFT plot appears normal, but performance is poor.

• Make sure you are using the appropriate band-pass filter on the analog input.

• Make sure the signal generators for the clock and the analog input are clean (low phase noise).

• If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.

• Make sure the SPI config file matches the product being evaluated.

• Make sure there isn't any extra stress/torque on the clock and analog input connectors.

The FFT window remains blank after the Run button is clicked

• Make sure the evaluation board is securely connected to the SDP-H1.

• Make sure the FPGA has been programmed by verifying that the FPGA_DONE LED is illuminated on the EVAL-SDP-CH1Z. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the SDP-H1setup process.

• Make sure the correct FPGA bin file was used to program the FPGA.

• Be sure that the correct sample rate is programmed. Click on the Settings button in the ADC Data Capture block in VisualAnalog, and verify that the Clock Frequency is properly set.

• Ensure that the ADC has a valid clock input

The AD9467-FMC-250EBZ is configured from the factory to use an external clock connected to J201. Alternatively, the AD9467-FMC-250EBZ can be configured to use the on-board 250MHz oscillator and AD9517-4 Clock Generator to generate the 250 Msps clock input. (Note: some boards have shipped with a 250 MHz oscillator and will require a different configuration)

Hardware Modifications

• Remove the following components: R209, R210, C209, C210

• Add the following components: C205, C206, C300, C301, C304, C305

• Make sure that Jumper P200 is on the “On” Position

Additional Software Needed

• configure_ad9517_AD9467-FMC-250EBZ MGP file

Setup Instructions

1. Make sure that a clock source is not connected to J201

2. Configure SPIcontroller and VisualAnalog as described above

3. Launch a 2nd instance of SPIController.

4. Load the AD9517spiR03.cfg configuration file.

5. Click Config>Controller Dialog

6. Select “2” Under FIFO Chip Sel #

   Figure 12. Select Fifo Chip Sel # 2 in SPIController

7. Click Apply and OK

8. Click File>Macro Group Open

9. Select the configure_ad9517_AD9467-FMC-250EBZ .mgp file

10. Check the Enable Check Box

    Figure 13. Select Enable Macro in SPIController

11. Click Run Macros

    Figure 14. Click Run Macros in SPIController

12. Make sure that LED CR300 is illuminated on the AD9467-FMC-250EBZ.

Obtaining an FFT

1. Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 9

   Figure 15. AD9467-FMC-250 FFT at 140.3MHz Analog Input (performance may be degraded compared to high-quality direct clock)